DSL Electronic Design

What is an FPGA? – Design Support

design1Introduction

A field-programmable gate array (FPGA) is an integrated circuit designed to have its operation configured subsequent to manufacturing, assembly and even deployment of a product of which it forms a part.

FPGAs contain programmable logic blocks, that are capable of performing many different operations from simple logic gates to complex functions, and memory blocks.

These blocks can then be connected using a hierarchy of reconfigurable interconnects.

The combination of these elements allows the FPGA to perform in many varied applications.

Advantages

The main advantage of an FPGA, over the equivalent discrete circuit or an Application Specific IC (ASIC) is the ability to easily change its functionality after a product has been designed.

In addition FPGA require a smaller board space and can be more energy efficient than the equivalent discrete circuit.

FPGA are more flexible than a Complex Programmable Logic Device (CPLD) as they, generally, include a greater amount of both logic blocks and programmable interconnects.

FPGA have a lower associated development cost than an ASIC. Whilst an ASIC can perform the same operations as an FPGA and are specific to the application, they cannot be reprogrammed.

FPGA will have a lower time-to-market than an ASIC and also will have a lower non-recurring engineering (NRE) cost.

Disadvantages

Due to the increased flexibility of an FPGA it will be less energy efficient and slower than either CPLDs or ASICs.

They are also be more complex to design than CPLDs. Not only due to their increased size but, due to the greater timing delays that the additional interconnect routes can add, it is more difficult to achieve the required interface signal timings for correct operation.

Historically CPLDs included internal non-volatile flash memory to load the configuration at power on, whilst FPGAs used external devices. FPGA are now available with this functionality, however.

The unit cost of FPGA is greater than that of both CPLD and ASIC.

Selection

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